Semiconductor device being capable of improving the breakdown characteristics

ABSTRACT

A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to Korean patent applicationnumber 10-2014-0038817, filed on Apr. 1, 2014, the entire disclosure ofwhich is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of Invention

Various exemplary embodiments of the present invention relate to asemiconductor device, and more specifically to a semiconductor deviceusing a high voltage.

2. Description of Related Art

Although the external voltage supplied to semiconductor device isgenerally low, a high internal voltage is still. To this end, thesemiconductor device internally generates and uses a high voltage.

However, there are breakdown characteristics as a result of internalhigh voltage applications which increase as size of the semiconductordevice becomes smaller. Worsening of the breakdown characteristicsdegrades the overall electrical characteristics of the semiconductordevice.

SUMMARY

Various exemplary embodiments of the present invention are directed to asemiconductor device with improved electrical characteristics for highvoltage applications.

One embodiment of the present invention provides a semiconductor deviceincluding a high-voltage supply circuit suitable for supplying a highvoltage; a discharge circuit suitable for discharging the high voltage;and an auxiliary-voltage supply circuit suitable for supplying a firstauxiliary voltage, which varies according to operation state of thehigh-voltage supply circuit, to a reference node of the dischargecircuit.

Another embodiment of the present invention provides a semiconductordevice including a high-voltage supply circuit suitable for supplying ahigh voltage; an auxiliary-voltage supply circuit suitable for supplyingan auxiliary voltage, which varies according to the operation state ofthe high-voltage supply circuit; and a transfer circuit suitable fortransferring an input voltage in response to the high voltage and theauxiliary voltage.

Still another embodiment of the present invention, provides asemiconductor device including a memory block including memory cells, ahigh-voltage supply circuit suitable for supplying a high voltage, anauxiliary-voltage supply circuit suitable for supplying a firstauxiliary voltage, which varies according to the operation state of thehigh-voltage supply circuit, and a transfer circuit connected betweenglobal lines and the local lines of the memory block, and suitable fortransferring operation voltages of the global lines to the local linesin response to the high voltage and the first auxiliary voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a block diagram illustrating a semiconductor device accordingto an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a high-voltage supply circuitshown in FIG. 1;

FIG. 3 is a block diagram illustrating an auxiliary-voltage supplycircuit shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating a transfer circuit shown inFIG. 1;

FIG. 5 is a circuit diagram illustrating a discharge circuit shown inFIG. 1;

FIG. 6 is a block diagram illustrating a semiconductor device accordingto an embodiment of the present invention;

FIG. 7 is a circuit diagram illustrating a high-voltage supply circuitand a discharge circuit shown in FIG. 6;

FIG. 8 is a block diagram illustrating a memory system according to anembodiment of the present invention;

FIG. 9 is a block diagram illustrating a fusion memory system accordingto an embodiment of the present invention; and

FIG. 10 is a block diagram illustrating a computing system according toan embodiment of the present invention.

DETAILED DESCRIPTION

Throughout the specification, it will be understood that when an elementis referred to as being “connected” or coupled to another element, itcan be directly connected or coupled to the other element or interveningelements may be present. Further, it will be further understood that theterms “comprises,” “comprising,” “includes,” and/or “including” whenused herein, specify the presence of stated features, items, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, items, steps,operations, elements, components, and/or groups thereof.

FIG. 1 is a block diagram illustrating a semiconductor device accordingto an embodiment. FIG. 2 is a block diagram illustrating a high-voltagesupply circuit shown in FIG. 1. FIG. 3 is a block diagram illustratingan auxiliary-voltage supply circuit shown in FIG. 1. FIG. 4 is a circuitdiagram illustrating a transfer circuit shown in FIG. 1. FIG. 5 is acircuit diagram illustrating a discharge, circuit shown in FIG. 1.

Referring to FIG. 1, the semiconductor device may include a high-voltagesupply circuit 10, a transfer circuit 20, a discharge circuit 30, and anauxiliary-voltage supply circuit 40. The semiconductor device mayinclude one or both of the transfer circuit 20 and the discharge circuit30.

The high-voltage supply circuit 10 may supply a high voltage Vhigh2. Theauxiliary-voltage supply circuit 40 may supply auxiliary voltages Vg,Vs, and Vhigh1 to the transfer circuit 20 and the discharge circuit 30.The transfer circuit 20 may transfer an input voltage Vin as an outputvoltage Vout in response to the high voltage Vhigh2 and the auxiliaryvoltage Vhigh1. The discharge circuit 30 may discharge an output node ofthe high-voltage supply circuit 10 in response to the auxiliary voltagesVg and Vs of the auxiliary-voltage supply circuit 40 when thehigh-voltage supply circuit 10 does not operate. Each configuration willbe described in detail below.

Referring to FIG. 2 the high-voltage supply circuit 10 may include ahigh-voltage supply control unit 110, and a high-voltage supply unit120. The high-voltage supply control unit 110 may output a controlsignal for controlling the high-voltage supply unit 120, for example, aninverted enable signal/EN. The high-voltage supply control unit 110 mayalso output an enable signal EN. The enable signal EN may be outputtedto other circuits such as the auxiliary-voltage supply circuit 120. Thehigh-voltage supply unit 120 may supply the high voltage Vhigh2 inresponse to the control signal/EN of the high-voltage supply controlunit 110.

Referring to FIG. 3, the auxiliary-voltage supply circuit 40 may supplythe auxiliary voltages Vg, Vs, and Vhigh1, each of which may havedifferent levels according to activation of the high-voltage supplycircuit 10, the transfer circuit 20, and the discharge circuit 30.

For example, the auxiliary-voltage supply circuit 40 may output anauxiliary voltage Vhigh1 having the same level as the high voltageVhigh2 when the high-voltage supply circuit 10 operates. In contrast,the auxiliary-voltage supply circuit 40 may output an auxiliary voltageVhigh1 having a lower level than the input voltage Vin when thehigh-voltage supply circuit 10 does not operate. Preferably, theauxiliary-voltage supply circuit 40 may output the auxiliary voltageVhigh1 having a level lower than the input voltage Vin and higher thanthe high voltage Vhigh2 when the high-voltage supply circuit 10 does notoperate.

When the high-voltage supply circuit 10 operates, the auxiliary-voltagesupply circuit 40 may apply the auxiliary voltage Vs having a positivepolarity with reference to a ground node of the discharge circuit 30. Incontrast when the high-voltage supply circuit 10 does not operate, theauxiliary-voltage supply circuit 40 may apply an auxiliary voltage Vshaving a ground level with reference to the ground node of the dischargecircuit 30.

Referring to FIG. 5, the discharge circuit 30 may be implemented with atransistor NT3, which may receive a high voltage Vhigh2 from thehigh-voltage supply circuit 10 at its drain, an auxiliary voltage Vsfrom the auxiliary-voltage supply circuit 40 at its source, and anauxiliary voltage Vg from the auxiliary-voltage supply circuit 40 at itsgate. The source of the transistor NT3 or the discharge circuit 30 forreceiving the auxiliary voltage Vs from the auxiliary-voltage supplycircuit 40 may be a ground node.

Referring back to FIG. 3, the auxiliary-voltage supply circuit 40 mayapply the auxiliary voltage Vg to the gate of a transistor NT3 of thedischarge circuit 30. For example, when the high-voltage supply circuit10 operates, the auxiliary-voltage supply circuit 40 may apply theauxiliary voltage Vg having a ground level to the gate of the transistorNT3 of the discharge circuit 30. Further, when the high-voltage supplycircuit 10 does not operate, the auxiliary-voltage supply circuit 40 mayapply the auxiliary voltage Vg having a positive polarity to the gate ofthe transistor NT3 of the discharge circuit 30. Here, theauxiliary-voltage supply circuit 40 may adjust the level of theauxiliary voltage Vg applied to the gate of the transistor NT3 so thatthe transistor NT3 is turned off when the high-voltage supply circuit 10operates, and the transistor NT3 is turned on when the high-voltagesupply circuit 10 does not operate. Specifically, the auxiliary-voltagesupply circuit 40 may apply the auxiliary voltage Vg, the level of whichis less than the sum of the auxiliary voltage Vs applied to the groundnode of the discharge circuit 30 and a threshold voltage of thetransistor NT3, to the gate of the transistor NT3 when the high-voltagesupply circuit 10 operates in order to turn off the transistor NT3 orthe discharge circuit 30.

The auxiliary-voltage supply circuit 40 may include a firstauxiliary-voltage supply unit 410 and a second auxiliary-voltage supplyunit 420. The first auxiliary-voltage supply unit 410 may supply theauxiliary voltages Vg and Vs to the discharge circuit 30 in response toa discharge signal DISCH. The second auxiliary-voltage supply unit 420may supply the auxiliary voltage Vhigh1 to the transfer circuit 20 inresponse to a control signal such as the enable signal EN.

The discharge signal DISCH input to the first auxiliary-voltage supplyunit 410 and the control signal EN input to the second auxiliary-voltagesupply unit 420 may be the same signal, and be provided from thehigh-voltage supply control unit 110 of the high-voltage supply circuit10. Therefore, the auxiliary voltages Vg, Vs, and Vhigh1 may beoutputted together to the transfer circuit 20 and the discharge circuit30 in response to the control signal EN.

Referring to FIG. 4, the transfer circuit 20 may transfer the inputvoltage Vin as the output voltage Vout in response to the high voltageVhigh2 of the high-voltage supply circuit 10, and the auxiliary voltageVhigh1, of the auxiliary-voltage supply circuit 40.

The transfer circuit 20 may include serially coupled first and secondtransistors NT1 and NT2. The first transistor NT1 may transfer the inputvoltage Vin to the second transistor NT1 in response to the auxiliaryvoltage Vhigh1 from the auxiliary-voltage supply circuit 40. The secondtransistor NT2 may transfer the output from the first transistor NT1 asthe output voltage Vout in response to the high voltage Vhigh2 from thehigh-voltage supply circuit 10.

It is preferable that the high voltage Vhigh2 and the auxiliary voltageVhigh1 are at least higher than the input voltage Vin by the thresholdvoltage of the second transistor NT2 and the first transistor NT1,respectively. That is, the output voltage Vout of the transfer circuit20 may be maintained at the same level as the input voltage Vin of thetransfer circuit 20.

Hereinafter, improvement of breakdown characteristics of thesemiconductor device in accordance with an embodiment of the presentinvention will be described. First, improvement of the breakdowncharacteristics of the transfer circuit 20 will be described.

Referring to FIGS. 1 and 4, the auxiliary-voltage supply circuit 40 mayoutput an auxiliary voltage Vhigh1 having the same level as the highvoltage Vhigh2 when the high-voltage supply circuit 10 operates or whenthe high voltage Vhigh2 is output. As a result, the transfer circuit 20may transfer the input voltage Vin as the output voltage Vout inresponse to the high voltage Vhigh2 and the auxiliary voltage Vhigh1.Because the high voltage Vhigh2 and the auxiliary voltage Vhigh1 may behigher than the input voltage Vin by the threshold voltages of thesecond and first transistors NT2 or NT1, respectively, the transfercircuit 20 may transfer the input voltage Vin as the output voltage Voutwithout a voltage drop, and the output voltage Vout may be maintained atthe same level as the input voltage Vin.

Assume that the transfer circuit 20 as a comparison example includes thesecond transistor NT2 only. When the high-voltage supply circuit 10 doesnot operate or when the high voltage Vhigh2 is not output, or ismaintained at a low level the high-voltage supply circuit 10 applies thevoltage Vhigh2 at a low level to the gate of the second transistor NT2of the transfer circuit 20 while the input voltage Vin having a highlevel is input to the drain of the second transistor NT2. The highvoltage difference between the voltages applied to the gate and drain ofthe second transistor NT2 causes a breakdown of the second transistorNT2.

In accordance with the embodiment of the present invention as shown inFIG. 4, when the high-voltage supply circuit 10 does not operate, theauxiliary-voltage supply circuit 40 may apply the auxiliary voltageVhigh1, which is lower than the input voltage Vin and higher than theoutput voltage Vhigh2 of the high-voltage supply circuit 10, to the gateof the first transistor NT1, and the breakdown characteristics of thesecond transistor NT2 may be improved. This will be described in detailbelow.

When the auxiliary-voltage supply circuit 40 applies an auxiliaryvoltage Vhigh1 lower than the input voltage Vin to the gate of the firsttransistor NT1, the first transistor NT1 may transfer a voltage lowerthan the auxiliary voltage Vhigh1 by the threshold voltage thereof. Thatis, the input voltage Vin may be applied to the first transistor NT1while a low voltage, which is the auxiliary voltage Vhigh1 minus thethreshold voltage Vth of the transistor NT1, i.e., Vhigh1−Vth, may betransferred to the second transistor NT2. Since the voltage Vhigh1−Vthlowered by the first transistor NT1 is applied to the second transistorNT2, the breakdown characteristics of the second transistor NT2 may beimproved by reducing the input voltage to the second transistor NT2.Thus the breakdown characteristics of the transistor circuit 20 and thesemiconductor device may be improved by the first transistor NT1 and theauxiliary voltage Vhigh1.

Improvement of breakdown characteristics of the discharge circuit 30will now be described.

Referring to FIG. 5, when the high-voltage supply circuit 10 does notoperate or when the high voltage Vhigh2 is not outputted, or ismaintained at a low level, the auxiliary-voltage supply circuit 40 mayapply an auxiliary voltage Vs having the ground level to the ground nodeof the discharge circuit 30. More specifically, the auxiliary-voltagesupply circuit 40 may apply an auxiliary voltage Vg having a positivepolarity to the gate of the transistor NT3 of the discharge circuit 30,and the auxiliary voltage Vs having the ground level to the ground nodeof the transistor NT3. The transistor NT3 is turned on by the auxiliaryvoltages Vg and Vs, and the high-voltage supply circuit 10 is normallydischarged.

When the high-voltage supply circuit 10 operates or when the highvoltage Vhigh2 is outputted, the operation of the discharge circuit 30is stopped. That is, the transistor NT3 of the discharge circuit 30should be turned off. Assume for a comparison example that the groundvoltage is applied to the source and gate of the transistor NT3 in orderto turn off the transistor NT3. In such a case, the high voltagedifference between the drain of the transistor NT3, to which the highvoltage Vhigh2 is applied, and the gate of the transistor NT3 is formedand a breakdown of the transistor NT3 may occur due to the high voltagedifference.

In order to prevent the breakdown of the transistor NT3 in accordancewith an embodiment of the present invention, the auxiliary-voltagesupply circuit 40 may supply auxiliary voltages Vg and Vs having apositive polarity to the discharge circuit 30. For example, theauxiliary-voltage supply circuit 40 may apply an auxiliary voltage Vshaving a positive polarity to the ground node of the discharge circuit30. More specifically, the auxiliary-voltage supply circuit 40 may applythe auxiliary voltage Vs having a positive polarity to the source of thetransistor NT3 corresponding to the ground node. Further, theauxiliary-voltage supply circuit 40 may also apply the auxiliary voltageVg of the positive polarity to the gate of the transistor NT3. In thiscase, it is preferable that the auxiliary-voltage supply circuit 40apply the auxiliary voltage Vg, which is lower than the sum of theauxiliary voltage Vs applied to the ground node, and a threshold voltageof the transistor NT3, to the gate of the transistor NT3 in order forthe transistor NT3 to remain turned-off.

As the auxiliary-voltage supply circuit 40 applies the auxiliaryvoltages Vg and Vs to the discharge circuit 30 with the aboveconditions, the transistor NT3 may remain turned-off while the voltagedifference between the gate of the transistor NT3 and the drain, towhich the high voltage Vhigh2 is applied, may be reduced. As a result,the breakdown characteristics of the second transistor NT3 included inthe discharge circuit 30 may be improved with the application of theauxiliary voltages Vg and Vs.

Hereinafter, a flash memory device as an example of the semiconductordevice in accordance with an embodiment of the present inventiondescribed above will be demonstrated. FIG. 6 is a block diagramillustrating a semiconductor device according to an embodiment of thepresent invention.

Referring to FIG. 6, the semiconductor device may include a memory blockMB and operation circuits 10 to 50. The operation circuits may include ahigh-voltage supply circuit 10, a transfer circuit 20, a dischargecircuit 30, an auxiliary-voltage supply circuit 40, and anoperation-voltage supply circuit 50. The high-voltage supply circuit 10,the transfer circuit 20, the discharge circuit 30, and theauxiliary-voltage supply circuit 40 shown in FIG. 6 may correspond tothe high-voltage supply circuit 10, the transfer circuit 20 thedischarge circuit 30 and the auxiliary-voltage supply circuit 40described above with reference to FIGS. 1 to 5. The operation-voltagesupply circuit 50 may output a signal corresponding to the input voltageVin described above with reference to FIGS. 1 to 5.

The memory block MB may include a plurality of memory strings STconnected between bit lines BL and a common source line SL. Memory cellsCe and Co may be connected to each word line WL0 to WLn. The memorystrings ST may be connected to the bit lines BL, respectively, andconnected in common to the common source line SL. Each memory string STmay include a source select transistor SST, having a source connected tothe common source line SL, a cell string, having a plurality of memorycells Ce connected in series, and a drain select transistor DST, havinga drain connected to the bit line BL. The memory cells Ce included inthe cell string are connected in series between the select transistorsSST and DST.

A gate of the source select transistor SST may be connected to a sourceselect line SSL, gates of the memory cells Ce and Co may be connected tothe word lines WL0 to WLn, and a gate of the drain select transistor DSTmay be connected to a drain select line DSL. The drain select transistorDST may control the connection or disconnection of the cell string Cewith the bit line, and the source select transistor may SST control theconnection or disconnection of the cell string Ce with the common sourceline SL.

In a NAND flash memory device, memory cells and flag cells included in amemory cell block may be classified in units of physical pages orlogical pages. For example, memory cells Ce and Co connected to one wordline (e.g. WL0) form one physical page. Even-numbered memory cells Ceconnected to one word line (e.g., WL0) may configure one even physicalpage, and odd-numbered memory cells Co may configure one odd physicalpage. The page (or, an even page and an odd page) may be the basic unitof a program operation or a read operation.

The high-voltage supply circuit 10 may output a high voltage Vhigh2 tothe transfer circuit 20. Specifically, in the flash memory device, eachmemory block MB may have the high-voltage supply circuit 10, thedischarge circuit 30, and the auxiliary-voltage supply circuit 40, andthe high-voltage supply circuit 10 may output the high voltage Vhigh2 inresponse to a coded address signal. This will be described in detailbelow.

FIG. 7 is a circuit diagram illustrating the high-voltage supply circuit10 and the discharge circuit 30 shown in FIG. 6.

Referring to FIG. 7, the high-voltage supply circuit 10 may include ahigh-voltage supply control unit 110 and a high-voltage supply unit 120.The high-voltage supply control unit 110 may include logic gates ND1 andND2, an inverter IV1, and a transistor THVN. Each of the logic gates ND1and ND2 may include a NAND gate.

The first logic gate ND1 may perform a logic NAND operation in responseto a plurality of decoded address signals XA, XB, XC, and XD. The secondlogic gate ND2 may output a control signal or an enable signal EN to anode SEL in response to an output signal of the first logic gate ND1 anda program precharge signal PGMPREb. The control signal EN may be appliedto the auxiliary-voltage supply circuit 40. The inverter IV1 may outputan inverted control signal or an inverted enable signal/EN by invertingthe voltage of the node SEL.

The transistor THVN transfers the voltage of the node SEL to an outputnode Q in response to a precharge signal PRE. The output node Q isprecharged by a voltage transferred through the transistor THVN.

The high-voltage supply unit 120 may include a depletion transistor DHVNand a high voltage P-channel Mosfet (PMOS) transistor HVP. The depletiontransistor DHVN and the high voltage PMOS transistor HVP may beconnected in series between a pumping voltage Vpp and the output node Q.A drain of the depletion transistor DHVN may be connected to the pumpingvoltage Vpp, and a gate of the depletion transistor DHVN may beconnected to the output node Q. The high voltage PMOS transistor HVP maybe connected between the depletion transistor DHVN and the output nodeQ, and may operate in response to the inverted enable signal/EN.

When the high voltage PMOS transistor HVP is turned on in response tothe inverted enable signal/EN, and the output node Q is precharged bythe voltage transferred through the depletion transistor THVN, thepumping voltage Vpp may be transferred to the output node Q, and thevoltage Vhigh2 of the output node Q may be increased to a high level.For example, the voltage Vhigh2 of the output node Q may be increased bythe electrical potential of the enable signal EN, and the depletiontransistor DHVN may transfer the pumping voltage Vpp to the high voltagePMOS transistor HVP in response to the voltage Vhigh2 of the output nodeQ. The depletion transistor DHVN having a negative threshold voltage maypass a certain amount of current even when the voltage Vhigh2 of theoutput node Q applied to the gate is 0 V. The high voltage PMOStransistor HVP may be turned on in response to the inverted enablesignal/EN and transfer the pumping voltage Vpp to the output node Q. Asa result, the voltage Vhigh2 of the output node Q may be furtherincreased. Because of this, the amount of current flowing through thedepletion transistor DHVN may be further increased, and the voltageVhigh2 of the output node Q may be increased to the level of the pumpingvoltage Vpp.

As described above, in the flash memory device in accordance with anembodiment of the present invention, the high-voltage supply circuit 10may output the high voltage Vhigh2 in response to the plurality ofdecoded address signals XA, XB, XC, and XD. That is, the high-voltagesupply circuit 10 may output the high voltage Vhigh2 only when thecorresponding memory block is selected according to the plurality ofdecoded address signals XA, XB, XC, and XD.

Referring again to FIG. 6, the transfer circuit 20 may be connectedbetween global lines GSSL, GWL0 to GWLn, and GDSL, and local lines SSL,WL0 to WLn, and DSL of the memory block MB, and may operate in responseto the high voltage Vhigh2 of the high-voltage supply circuit 10 and theauxiliary voltage Vhigh1 of the auxiliary-voltage supply circuit 40.That is, the transfer circuit 20 may perform an operation for connectingthe global lines GSSL, GWL0 to GWLn, and GDSL to the local lines SSL,WL0 to WLn, and DSL of the selected memory block MB in response to thehigh voltage Vhigh2 and the auxiliary voltage Vhigh1. That is, operationvoltages (e.g., a program voltage, an erase voltage, a read voltage, apass voltage, a verify voltage, etc.), which are output from theoperation-voltage supply circuit 50 to the global lines GSSL, GWL0 toGWLn, and GDSL, may be transferred to the local lines SSL, WL0 to WLn,and DSL of the selected memory block MB.

The transfer circuit 20 may include transistors NT1 and NT2 connected inseries between each of the global lines GSSL, GWL0 to GWLn and GDSL, andeach of the local lines SSL, WL0 to WLn and DSL. The transistor NT1 mayoperate in response to the auxiliary voltage Vhigh1, and the transistorNT2 may operate in response to the high voltage Vhigh2.

The discharge circuit 30 may be connected to the output node Q of thehigh-voltage supply circuit 10 and may perform an operation fordischarging the output node Q when the high-voltage supply circuit 10does not operate.

The auxiliary-voltage supply circuit 40 may output the auxiliary voltageVhigh1 to the transfer circuit 20, and the auxiliary voltages Vs and Vgto the discharge circuit 30. Specifically, the auxiliary-voltage supplycircuit 40 may output the auxiliary voltage Vhigh1 to the transfercircuit 20 in response to the control signal EN generated according tothe coded address signals received from the high-voltage supply circuit10. That is, only when the corresponding memory block MB is selectedaccording to the plurality of decoded address signals XA, XB, XC, andXD, may the auxiliary-voltage supply circuit 40 output the auxiliaryvoltage Vhigh1 in response to the control signal EN.

Thus, since the high voltage Vhigh2 and the auxiliary voltage Vhigh1 areoutput only when the corresponding memory block MB is selected accordingto the plurality of decoded address signals XA, XB, XC, and XD, may thehigh voltage Vhigh2 and the auxiliary voltage Vhigh1 correspond to ablock select signal indicating that the memory block is selected.

The operation-voltage supply circuit 50 may output the operationvoltages required for a program operation, a read operation, and anerase operation of the memory cells to the global lines GSSL, GWL0 toGWLn, and GDSL.

The transfer circuit 20 may transfer the operation voltages of theglobal lines GSSL, GWL0 to GWLn, and GDSL to the local lines SSL, WL0 toWLn, and DSL of the selected memory block MB from a plurality of memoryblocks (not illustrated) in response to the high voltage Vhigh2 of thehigh-voltage supply circuit 10 and the auxiliary voltage Vhigh1 of theauxiliary-voltage supply circuit 40.

While the high-voltage supply circuit 10 supplies the high voltageVhigh2 to the transfer circuit 20, the auxiliary-voltage supply circuit40 may output the auxiliary voltages Vs and Vg to the discharge circuit30 for improving the breakdown characteristics of the discharge circuit30. Further, the auxiliary-voltage supply circuit 40 may output theauxiliary voltage Vhigh1 to the transfer circuit 20 for improving thebreakdown characteristics of the transfer circuit 20.

Through the above configuration and operations, overall breakdowncharacteristics of a flash memory device may be improved, and thus theflash memory device may stably operate.

FIG. 8 is a block diagram illustrating a memory system according to anembodiment of the present invention.

Referring to FIG. 8, a memory system 800 according to the embodiment ofthe present invention may include a non-volatile memory device (NVM) 820and a memory controller 810.

The NVM device 820 may include the semiconductor device illustrated inFIG. 1 or 6. The memory controller 810 may control the NVM device 820.As the NVM device 820 of the memory system 800 may include thesemiconductor device described above, operational characteristics of thememory system 800 may be improved.

A memory card or a semiconductor disk device (a solid state disk (SSD))comprised of a combination of the NVM device 820 and the memorycontroller 810 may be provided. Static random access memory (SRAM) 811may be used as an operational memory of a central processing unit (CPU)812. A host interface (I/F) 813 may provide a data exchange protocol fora host Host connected to the memory system 800. An error correctionblock (ECC) 814 detects and corrects errors included in data read fromthe non-volatile memory device 820. A memory I/F 815 may interface withthe NVM device 820 of the present invention. The CPU 812 may performvarious control operations for data exchange of the memory controller810.

Although not shown in the drawings, it is apparent to those skilled inthe art that the memory system 800 of the present invention may furtherhave a read only memory (ROM) (not shown) and the like configured tostore code data for interfacing with the host Host. The NVM device 820may be implemented as a multi-chip package constituted of a plurality offlash memory chips. The memory system 800 of the present invention maybe embodied as a storage medium having a low probability of erroroccurrence and high reliability. Particularly in the memory system suchas a semiconductor disk device (that is, an SSD) in which recentresearch is being actively conducted, the flash memory device having anembodiment of the present invention may be included. In this case, thememory controller 810 may communicate with the outside (e.g., a hostHost) through one of various interface protocols such as a UniversalSerial Bus (USB) protocol, a multimedia card (MMC) protocol, aperipheral component interconnect express (PCI-E) protocol, a serialadvanced technology attachment (SATA) protocol, a parallel-ATA (PATA)protocol, an enhanced small disk interface (ESDI) protocol, anintegrated drive electronics (IDE) protocol, and so on.

FIG. 9 is a block diagram illustrating a fusion memory system accordingto an embodiment of the present invention. For example, technicalcharacteristics of the semiconductor device described above may beapplied to a OneNAND flash memory device 900 as a fusion memory device.

The OneNAND flash memory device 900 may include a host I/F 910configured to exchange information with a device using differentprotocols, a buffer RAM 920 configured to have an embedded code fordriving the memory device or temporarily storing data, a controller 930configured to control a read operation, a program operation, and allstates in response to a control signal and a command received from theoutside, a register 940 configured to store data such as a command, anaddress, configuration data, which defines the system operationalenvironment inside the memory device, and so on, and a NAND flash cellarray 950 having an operational circuit including an NVM cell and aread/write circuit.

FIG. 10 is a block diagram illustrating a computing system according toan embodiment of the present invention.

A computing system 1000 of the present invention may include a CPU 1020(i.e., microprocessor), a RAM 1030, a user interface 1040, a modem 1050such as a baseband chipset, and a memory system 1010, which are allelectrically connected to a system bus 1060. When the computing system1000 of the present invention is a mobile device, a battery (not shown)may be further provided to supply an operational voltage to thecomputing system 1000. Although not shown in the drawings, it isapparent to those skilled in the art that an application chipset, acamera image processor (CIS), a mobile DRAM, and so on may be furtherprovided in the computing system 1000 of the present invention. Thememory system 1010, for example, may have an SSD using theabove-described semiconductor device in order to store data.Alternatively, the memory system 1010 may be provided as a fusion flashmemory (e.g., an OneNAND flash memory).

The embodiments of the present invention can improve the electricalcharacteristics in high voltage applications.

In the drawings and specification, exemplary embodiments of theinvention have been disclosed. Although specific terms are employed,they to be understood in a generic and descriptive sense only and notfor purpose of limiting the scope of the current invention. As for thescope of the invention, it is to be set forth by the following claims.Therefore, it will be understood by those of ordinary skill in the artthat various changes in form and detail may be made without departingfrom the spirit and scope of the present invention as defined by thefollowing claims.

1-12. (canceled)
 13. A semiconductor device, comprising: a memory blockincluding memory cells; a high-voltage supply circuit suitable forsupplying a high voltage; an auxiliary-voltage supply circuit suitablefor supplying a first auxiliary voltage, which varies according to anoperation state of the high-voltage supply circuit; and a transfercircuit connected between global lines and local lines of the memoryblock, and suitable for transferring operation voltages of the globallines to the local lines in response to the high voltage and the firstauxiliary voltage.
 14. The semiconductor device of claim 13, wherein theauxiliary-voltage supply circuit supplies the first auxiliary voltagehaving the same level as the high voltage when the high-voltage supplycircuit operates, and the first auxiliary voltage having a lower levelthan the input voltage when the high-voltage supply circuit does notoperate.
 15. The semiconductor device of claim 13, wherein the transfercircuit includes: a first transistor suitable for transferring theoperation voltages in response to the first auxiliary voltage; and asecond transistor suitable for outputting the transferred operationvoltages from the first transistor to the local lines in response to thehigh voltage.
 16. The semiconductor device of claim 13, furthercomprising a discharge circuit suitable for discharging the highvoltage, wherein the auxiliary-voltage supply circuit supplies a secondauxiliary voltage, which varies according to the operation state of thehigh-voltage supply circuit, to a reference node of the dischargecircuit.
 17. The semiconductor device of claim 16, wherein theauxiliary-voltage supply circuit supplies the second auxiliary voltagehaving a positive polarity to the reference node when the high-voltagesupply circuit operates, and wherein the auxiliary-voltage supplycircuit supplies the second auxiliary voltage having a ground level tothe reference node when the high-voltage supply circuit does notoperate.
 18. The semiconductor device of claim 16, wherein the dischargecircuit includes a transistor having the reference node.
 19. Thesemiconductor device of claim 18, wherein the auxiliary-voltage supplycircuit supplies the second auxiliary voltage of a positive polarity tothe reference node, and a third auxiliary voltage of a positive polarityto a gate of the transistor when the high-voltage supply circuitoperates, and wherein the auxiliary-voltage supply circuit supplies thesecond auxiliary voltage having a ground level to the reference node,and the third auxiliary voltage having a ground level to the gate of thetransistor when the high-voltage supply circuit does not operate. 20.The semiconductor device of claim 13, wherein the auxiliary-voltagesupply circuit operates in response to a control signal generated in thehigh-voltage supply circuit.